Siemens EDA Forum
Seoul 2024

Engineer a smart future with   Siemens EDA


  • Time
  • Session
  • 9:00 – 10:00
  • 등록 및 데모부스 관람

  • 10:00 - 10:10
  • Welcome Speech 

    김준환 대표이사 Siemens EDA

  • 10:10 - 10:50
  • Siemens EDA Keynote Speech : Enabling Imagination - A New Era of System Design

    Exploding societal demand for semiconductor-enabled products means that semiconductors are now a central part of the worldwide geopolitical discussion. With semiconductors now driving core product differentiation in virtually all areas, broad availability of high-quality leading-edge semiconductor processes and an advanced heterogeneous packaging ecosystem is critical to your success. Let’s explore how Siemens are delivering advanced manufacturing, AI enhanced design automation tooling, and open ecosystem enablement – to enable your next generation of designs.


    Mike Ellow CEO, Siemens EDA Silicon Systems

    Mike Ellow is CEO, Siemens EDA Silicon Systems, Siemens Digital Industries Software, a business unit of Siemens Digital Industries. He leads Siemens EDA (formerly Mentor Graphics) Integrated Circuit Solutions (ICS) R&D, as well as EDA Global Sales. Ellow has led Siemens EDA Sales since August 2014 and Siemens EDA ICS R&D since 2023. He brings 30 years of executive sales and technical management experience, along with a proven track record of building strong sales and engineering teams while delivering positive, predictable results. These results are built on a foundation of focusing on customer success. Ellow joined Mentor Graphics in March 2014 as part of the company’s acquisition of Berkeley Design Automation, where he was Vice President of Worldwide Sales. Prior to that, he held various positions at Cadence Design Systems, overseeing sales in North America, Europe, and India, culminating in the role of Corporate Vice President, North American Sales. Prior to Cadence, he held management, marketing, and engineering positions in a number of different industries. He started his career as an electrical engineer at Hughes Aircraft. Ellow has a BSEE from Lehigh University, an MSEE from the University of Southern California, and an MBA from California State University, Fullerton
  • 10:50 - 11:15
  • Invited Keynote Speech - Samsung Foundry

  • 11:15 - 11:40
  • Invited Keynote Speech - LG Electronics

  • 11:40 - 13:00
  • 점심식사 및 데모부스 관람

Technical Sessions

  • 13:00-13:30
  • Catapult HLS : Accelerating Neural Network Design at BlueDot for Better Visual Quality

    최근 몇 년 동안 효율적인 신경망 구현에 대한 수요가 기하급수적으로 증가했습니다. High Level Syntheis툴인 Catapult HLS는 이 분야의 게임 체인저로 부상했습니다. DNN(심층 신경망) 기반의 이미지/비디오 처리 IP인 Catapult HLS를 사용하여 PQO를 성공적으로 설계한 BlueDot의 사례는 Catapult HLS가 어떻게 신경망 설계를 가속화하여 출시 시간을 단축하고 성능을 향상시키는지 보여줍니다.

    In recent years, the demand for efficient neural network implementations has grown exponentially. Catapult HLS, a high-level synthesis tool, has emerged as a game-changer in this domain. BlueDot’s successful design of PQO using Catapult HLS—an Image/Video processing IP based on DNN (Deep Neural Network)—demonstrates how Catapult HLS accelerates neural network designs, enabling faster time-to-market and improved performance.


    Ungwon Lee, BlueDot
    Ansun Jeong, Siemens EDA

    Ungwon Lee
    Majored in electronic engineering at Inha University, Korea. He worked as a H/W engineer designing digital logic at LG Display for 8 years, and has currently been working at Bluedot for 4 years developing video codecs and video AI models as H/W architect and logic designer.

    Ansun Jeong
  • 13:30-14:00
  • Defect modeling based on actual defect in Samsung Foundry through UDFM and diagnosis flow improvement

    공정 레시피가 복잡해지면서 기존 공정에서 발생하지 않던 새로운 유형의 불량이 지속적으로 발생하고 있으며, 주요 불량이 되고 있습니다. 삼성 파운드리는 지멘스와 협업하여 다양한 불량을 1:1로 정확하게 모델링할 수 있는 플로우를 개발 및 개선하고 실제 제품에서 그 효과를 검증하고 있습니다. 이번 발표에서는 기존 결함 기반 불량 모델링의 한계를 소개하고, 협업을 통해 개선된 모델링 및 불량 분석 적용 플로우를 소개합니다. 개발된 플로우를 통해 기존 모델링에서 정확히 일치하지 않거나 커버하지 못했던 실제 결함까지 ATPG/진단 플로우에서 고려할 수 있게 되었습니다. 체적 진단 측면에서는 보다 높은 해상도의 분석 결과를 도출할 수 있을 것으로 보입니다.

    As process recipes become more complex, additional types of defects that did not occur in existing processes are continuously being created and are appearing as major defects. Samsung Foundry is collaborating with Siemens to develop and improve a flow that can accurately model various defects one-to-one and is verifying the effect in actual products. In this presentation, we introduce the limitations of existing fault-based defect modeling and introduce improved modeling and defect analysis application flow through collaboration. Through the developed flow, actual defects that were not accurately matched or covered in existing modeling can now be considered in the ATPG/diagnosis flow. In terms of volume diagnosis, it appears that higher resolution analysis results can be derived.


    Jaeseok Park, Samsung Electronics

  • 14:00 - 14:30
  • Understanding Power and Dynamic IR Drop for DFT Patterns Pre-Silicon Using Veloce

    DFT 패턴의 전력 관리는 칩의 고밀도, 기술 노드의 발전에 따른 VDD 축소 속도 저하, DFT 패턴의 높은 활동성으로 인해 발생하는 중요한 문제입니다. 일반적으로 DFT 패턴은 전력 관련 문제와 동적 IR 강하 문제로 인해 테스터에서 실패합니다. 이 세션에서는 선도적인 하드웨어 지원 검증 플랫폼인 Veloce를 사용하여 테스트용 설계(DFT) 패턴과 관련된 전력 영향 및 동적 IR 강하 효과를 다룹니다. DFT 패턴은 일반적으로 기능 패턴에 비해 3~4배 더 많은 활동을 생성하지만, 전력 공급 네트워크는 주로 기능 패턴을 지원하도록 설계되었습니다. 이러한 불일치는 종종 테스터의 테스트 실패로 이어져 테스트 통과를 위해 수정이 필요합니다.

    Veloce를 활용하여 포괄적인 pre-silicon 분석을 수행하여 다양한 DFT 패턴에 의해 유발되는 전력 소비 및 IR 강하 특성을 평가합니다. 전력 관련 문제를 조기에 발견하고 완화하는 것이 중요하다는 것을 입증하고, 전력 효율과 IR 강하 감소를 위한 pre-silicon DFT 패턴을 식별하고 해결할 수 있는 방법론을 제시합니다. Veloce DFT 앱을 사용하면 기존 시뮬레이션보다 수천 배 빠른 속도로 DFT 패턴을 실행할 수 있습니다. Veloce Power 앱과 Veloce IR 드롭 툴은 리버티, 활동 및 SPEF 파일을 사용하여 상세한 분석을 수행하여 DFT 패턴에 대한 정확하고 통찰력 있는 정보를 제공합니다. 이 솔루션은 DFT 및 테스트 엔지니어가 pre-silicon 검증 프로세스를 개선하고 신뢰할 수 있는 DFT 패턴을 보장하며 테스트 시간을 단축할 수 있는 유용한 프레임워크를 제공합니다.

    "Power management of DFT patterns is a significant problem driven by the high density of chips, the slowdown of VDD shrinkage with advancing technology nodes, and the high activity of DFT patterns. Commonly, DFT patterns fail on the tester due to power-related issues and dynamic IR drop challenges. This session addresses the power implications and dynamic IR drop effects associated with Design for Test (DFT) patterns using Veloce, the leading hardware assisted verification platform. DFT patterns typically create 3 to 4 times more activity compared to functional patterns, yet the power delivery network is primarily designed to support functional patterns. This discrepancy often leads to test failures on the tester, necessitating modifications to ensure tests pass.

    By leveraging Veloce's capabilities, we conduct comprehensive pre-silicon analyses to evaluate the power consumption and IR drop characteristics induced by various DFT patterns. We demonstrate the importance of early detection and mitigation of power-related issues, presenting methodologies to identify and remedy DFT patterns for power efficiency and IR drop reduction pre-silicon. The Veloce DFT app allows for running DFT patterns thousands of times faster than traditional simulation. The Veloce Power App and Veloce IR Drop tool perform detailed analyses using Liberty, activity, and SPEF files to provide accurate and insightful information for DFT patterns. This solution offers a valuable framework for DFT and test engineers to enhance pre-silicon verification processes, ensure reliable DFT patterns, and reduce test time. "


  • 14:30 - 14:50
  • 커피브레이크 및 데모부스 관람

  • 14:50 - 15:20
  • Marker based P2PCD: Easy efficient verification for P2P/CD measurements at desired layout points using Calibre PERC

    CalibreKR CheckStore에서 Calibre PERC를 사용해 개발된 마커 기반 P2PCD의 간편하고 효율적인 기능을 확인하세요. 이 강력한 기능을 사용하면 짧은 런타임으로 레이아웃의 특정 지점에서 P2P 및 CD 측정값을 쉽게 확인할 수 있습니다. 마커 기반 P2PCD의 다양한 기능을 살펴보고 LG전자가 수행한 실제 사례 연구를 통해 알아보세요.

    Discover the simplicity and efficiency of Marker Based P2PCD, a feature developed using Calibre PERC, in CalibreKR CheckStore. This powerful feature makes it easy to verify P2P and CD measurements at specific points on a layout, all with a short runtime. Join us as we explore the various functionalities of Marker Based P2PCD and learn from real-world case studies conducted by LG Electronics.


    Minsun Kim, LG Electronics
    Sean Byun, Siemens EDA

    Minsun Kim

    Sean Byun
  • 15:20 - 15:50
  • Avery Verificaiton IP


  • 15:50 - 16:20
  • 경품추첨 및 맺음말